Bump structures for low temperature chip bonding
US12354988B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2022 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Sep 2, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/81203
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a multi-chip system is disclosed. The method includes forming one or more bumps on respective conductive contact pads of a first electronic device, forming one or more mini-bumps on respective conductive contact pads of a second electronic device, and aligning respective one or more mini-bumps with respective one or more bumps. The method further includes performing a bump bonding process that exerts compression force on one or both the first electronic device and the second electronic device to compress the one or more mini-bumps into the one or more bumps to form one or more bump bond structures that bond the second electronic device to the first electronic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.