Semiconductor devices and data storage systems including the same
US12355003B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2022 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Aug 14, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device including a substrate, first pad layers and a second pad layer on the substrate, a pattern structure including first openings on the first pad layers and a second opening on the second pad layer, and having first and second regions, gate electrodes on the pattern structure and each including a pad region, channel structures penetrating through the gate electrodes in the first region, gate contact plugs electrically connected to the gate electrodes through the pad region of each of the gate electrodes and extending in a vertical direction to penetrate the first openings and connected to the first pad layers, a source contact plug, extending in the vertical direction penetrating the second opening and connected to the second pad layer, and a source connection patter under the pattern structure and in contact with the source contact plug and the second pad layer may be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.