Semiconductor package and method of fabricating the same
US12355005B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2022 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Jul 19, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06582
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a substrate that includes a plurality of vias, a first chip stack on the substrate and including a plurality of first semiconductor chips that are sequentially stacked on the substrate, and a plurality of first non-conductive layers between the substrate and the first chip stack and between neighboring first semiconductor chips. Each of the first non-conductive layers includes first extensions that protrude outwardly from first lateral surfaces of the first semiconductor chips. The more remote the first non-conductive layers are from the substrate, the first extensions protrude a shorter length from the first lateral surfaces of the first semiconductor chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.