SRAM memory cell device comprising ferroelectric access and storage transistors
US12356600B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Mar 24, 2022 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Mar 24, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/223
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random-access memory (SRAM) cell including a transistor is introduced. The transistor includes substrate and gate stack structure disposed over the substrate, in which the gate stack structure includes a gate oxide layer, a ferroelectric layer, and a conductive layer. The gate oxide layer is disposed over the substrate; the ferroelectric layer is disposed over the gate oxide layer, wherein the ferroelectric layer has a negative capacitance effect; and the first conductive layer, disposed over the ferroelectric layer. A method of adjusting a threshold voltage of a transistor in the SRAM is also introduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.