High electron mobility transistor with doped semiconductor region in gate structure
US12356653B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2024 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Feb 16, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/411
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes providing a semiconductor body including a plurality of two-dimensional charge carrier gas channels, forming a gate fin by forming a pair of gate trenches in an upper surface of the semiconductor body, the pair of gate trenches exposing each one of two-dimensional charge carrier gas channels, providing source and drain contacts that are electrically connected to each one of the plurality of two-dimensional charge carrier gas channels, providing a gate structure that is configured to control a conductive connection between the source and drain contacts, wherein providing the gate structure includes forming a layer of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and forming a conductive gate electrode on top of the layer of doped type III-nitride semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.