Method for semiconductor device interface circuitry functionality and compliance testing
US12360162B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2024 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Jun 5, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R35/00
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method is provided for determining a decoupling capacitance of a device under test (DUT) interface circuitry, which is between automated testing equipment (ATE) and a DUT. The method: disconnects the DUT from the DUT interface circuitry; connects a Device Under Testing Power Supply (DPS) resource as a DUT Power Supply to the DUT interface circuitry; sets a current clamp of the DPS resource to a test application level; turns off the DPS resource voltage; sets the DPS resource to a force voltage mode; sets the current clamp to a minimum current level; turns on the output; waits a period of time to allow the decoupling capacitance to charge; places the DPS resource into a voltage measurement mode; adds any delay time to the period of time; measures the voltage before the capacitance is fully charged; and determines the decoupling capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.