Method and apparatus to reduce memory in a NAND flash device to store page related information
US12360669B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Feb 9, 2023 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Feb 9, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The size of page map memory in a NAND flash device used to store page related information is decreased by embedding page type in a row address. The row address is received by the NAND flash device from the host on the data bus in a six-cycle sequence. The received row address is used to decode a physical page address received during the row address cycle to obtain a word line and a block segment number for a block segment in the word line in the NAND flash array. A same block segment number is used for each page type in the block segment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.