Reconfigurable cache architecture and methods for cache coherency
US12360902B2 · kind B2 · utility
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25Claims
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Key dates
| Filing date | Aug 4, 2023 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Aug 4, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for cache coherency in a reconfigurable cache architecture is provided. The method includes receiving a memory access command, wherein the memory access command includes at least an address of a memory to access; determining at least one access parameter based on the memory access command; and determining a target cache bin for serving the memory access command based in part on the at least one access parameter and the address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.