Dynamic clock tree planning using feedtiming cost
US12361194B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2022 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Mar 1, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device identifies a first clock tree topology for a circuit design, the first clock tree topology having a threshold feedthrough count and a first timing solution. The processing device further identifies one or more additional clock tree topologies for the circuit design, each of the one or more additional clock tree topologies having a different respective feedthrough count that is less than the threshold feedthrough count, and each of the one or more additional clock tree topologies comprising a respective timing solution. In addition, the processing device receives a selection of at least one of the first clock tree topology or the one or more additional clock tree topologies, and generates the circuit design according to the selection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.