Patent · US Active

DRC test pattern generation method and apparatus, electronic device, and storage medium

US12361196B2 · kind B2 · utility

0Cited by

0References

9Claims

0Family size

Assignee

CHANGXIN MEMORY TECHNOLOGIES, INC. · CN

Inventors

Chuanjiang Chen · Hefei, CN
Li Bai · Hefei, CN
Kang Zhao · Hefei, CN

Key dates

Filing date	Apr 8, 2022
Grant date	Jul 15, 2025
Priority date	—
Expiry date	Feb 21, 2044

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/18
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A DRC test pattern generation method includes: receiving a DRC test pattern generation request, the DRC test pattern generation request carrying the number of correct patterns and the number of erroneous patterns; acquiring layout design rule information and corresponding layer configuration information, the layer configuration information including process layer configuration parameter information that is set according to a process type; parsing parameter information corresponding to each rule in the layout design rule information and the process layer configuration parameter information in the layer configuration information, and generating formatted parameter information corresponding to the each rule; and generating a corresponding number of correct patterns and a corresponding number of erroneous patterns corresponding to each rule according to the formatted parameter information.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.