Tamper sensor for 3-dimensional die stack
US12361808B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2023 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Nov 1, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06541
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit die stack and method thereof are described herein that is capable of detecting a physical tampering event. The integrated circuit die stack includes a first integrated circuit die including a sensor network that extends substantially across an entire top surface of the first integrated circuit die, and a second integrated circuit die stacked below the first integrated circuit die. The second integrated circuit die is configured to receive sensing signals generated by the sensor network via a plurality of through-silicon-vias coupled with the first integrated circuit die and the second integrated circuit die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.