Memory circuit and method of operating same
US12362010B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 26, 2023 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Oct 27, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a control circuit coupled to the word line driver circuit. The control circuit is configured to delay a leading or falling edge of a word line signal in response to at least a first clock signal. The control circuit includes a first clock circuit configured to generate a second clock signal in response to a first reset signal and a clock signal, and an adjustable delay circuit configured to adjust a delay between the second and third clock signal in response to the second clock signal and an enable signal. The third clock signal is a delayed version of the second clock signal. An amount of the delay between the second and third clock signal is based on a voltage difference between a first supply voltage having a first swing, and a second supply voltage having a second swing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.