Memory device with reduced area
US12362017B2 · kind B2 · utility
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Key dates
| Filing date | Apr 11, 2024 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Apr 11, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of word lines (WLs) above a substrate; a plurality of memory strings laterally isolated from each other, each of the plurality of memory strings being operatively coupled to a respective subset of the plurality of WLs; and a plurality of drivers, each of the plurality of drivers being configured to control a corresponding one of the plurality of WLs and including a first transistor having a first conductive type and a second transistor having a second conductive type opposite to the first conductive type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.