Integrated circuit (IC) packages employing supplemental metal layer coupled to embedded metal traces in a die-side embedded trace substrate (ETS) layer, and related fabrication methods

US12362269B2 · kind B2 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Michelle Yejin Kim · San Diego, US
• Kuiwon Kang · San Diego, US
• Joan Rey Villarba BUOT · Escondido, US
• Ching-Liou Huang · Hengshan, TW

Key dates

• Filing date: Oct 18, 2021
• Grant date: Jul 15, 2025
• Expiry date: Aug 4, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2224/16225
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Integrated circuit (IC) packages employing a supplemental metal layer coupled to embedded metal traces in a die-side embedded trace substrate (ETS) layer to reduce metal density mismatch, and related fabrication methods. An IC package includes a semiconductor die (“die”) electrically coupled to a package substrate. The package substrate includes a die-side ETS metallization layer adjacent to and coupled to the die. To reduce or avoid metal density mismatch between the die-side ETS metallization layer and another metallization layer(s) in the package substrate, a supplemental metal layer with additional metal interconnects is disposed adjacent to the die-side ETS metallization layer. The additional metal interconnects are coupled in a vertical direction to the embedded metal traces in the die-side ETS metallization layer to increase metal density of die-side metal interconnects formed by the additional metal interconnects coupled to the embedded metal traces in the die-side ETS metallization layer.