Semiconductor device
US12362743B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 8, 2023 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Jul 28, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0072
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A first P-type transistor and a second P-type transistor are connected in series between a power supply terminal and an output terminal. A first N-type transistor and a second N-type transistor are connected between a ground terminal and a power supply terminal. The second N-type transistor and the second P-type transistor are complementarily turned on and off in accordance with an input signal. A gate voltage control circuit changes at least one of the gate voltage of the P-type transistor whose drain is electrically connected to the output terminal and the gate voltage of the N-type transistor by following the output voltage VOUT of the output terminal while keeping the P-type transistor or the N-type transistor on-states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.