Field programmable platform array
US12366882B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2021 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | May 8, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) chip including clock generation circuitry to generate a clock signal. Clock interface circuitry is coupled to the clock generation circuitry and includes multiple transmit pins that are distributed across a mounting surface of the IC chip. Each of the multiple transmit pins is configured to transmit a respective version of the clock signal to one or more off-chip devices. Multiple receiver pins are distributed across the mounting surface of the IC chip and correspond to the multiple transmit pins. Each of the multiple receiver pins is configured to receive respective arrival clock signals from the one or more off-chip devices. Delay compensation circuitry is coupled to the clock interface circuitry and includes multiple delay circuits. Each delay circuit is configured to delay a given clock signal fed to a given transmit pin by a given delay value to establish global timing alignment of the arrival clock signals at the one or more external devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.