Data layout configurations for access operations
US12366995B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2023 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | Dec 27, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for data layout configurations for access operations are described. The memory system may write data to a first set of memory cells using a first write operation having a first type of layout for mapping the data to physical addresses of the memory system in response to receiving a write command. The first set of memory cells may be written to as single-level cells (SLCs), multi-level cells (MLCs), or triple-level cells (TLCs). The memory system may transfer the data to a second set of memory cells of the memory system using a second write operation having the first type of layout. The second set of memory cells may be written to as quad-level cells (QLCs). The memory system may read the data from the second set of memory cells using a read operation having a second type of layout different than the first type of layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.