Debug trace circuitry configured to generate a record including an address pair and a counter value
US12367047B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 6, 2023 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | Feb 8, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30058
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed for debug path profiling. For example, a processor pipeline may execute instructions. A debug trace circuitry may, responsive to an indication of a non-sequential execution of an instruction by the processor pipeline, generate a record including an address pair and one or more counter values. The address pair may include a first address corresponding to a first instruction before the non-sequential execution and a second address corresponding to a second instruction resulting in the non-sequential execution. The one or more counter values may indicate, for example, a count of instructions executed, a type of instruction executed, cache misses, cycles consumed by cache misses, translation lookaside buffer misses, cycles consumed by translation lookaside buffer misses, and/or processor stalls.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.