Page buffer circuit with bit line select transistor

US12367936B2 · kind B2 · utility

Assignee

• YANGTZE MEMORY TECHNOLOGIES CO., LTD. · CN

Inventors

• Teng CHEN · 红钢城街道, CN
• Yan Wang · 红钢城街道, CN
• Jing Wei · Daguantang, CN
• Yang Zhang · San Diego, US
• Kuriyama Masao · 红钢城街道, CN

Key dates

• Filing date: Jan 20, 2023
• Grant date: Jul 22, 2025
• Expiry date: Jan 20, 2043

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C16/26
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Aspects of the disclosure provide a memory device. For example, the memory device can include a memory array, a bit line and a buffer. The memory array can include a plurality of memory strings. The memory strings can be divided into a first memory string group and a second memory string group. The bit line can include a first bit line segment coupled to the first memory string group and a second bit line segment coupled to the second memory string group. The buffer can be coupled to the memory array by the bit line. The memory array and the buffer can be included in separate first and second dies, respectively, and the first die can be bonded to the second die.