Simultaneous filling of variable aspect ratio single damascene contact to gate and trench vias with low resistance barrierless selective metallization
US12368095B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Sep 24, 2021 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | Nov 22, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53252
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure comprises a first metal layer having first conductive features. A second metal layer has second conductive features. A via layer is in an insulating layer between the first metal layer and the second metal layer. First vias and second vias are formed in the insulating layer. The first vias have a first aspect ratio greater than a second aspect ratio of the second vias. A barrier-less metal partially fills the first vias and fills the second vias. A pure metal fills a remainder of the first vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.