Semiconductor device
US12368443B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2023 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | Jul 11, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a phase splitter configured to output a plurality of clock signals having different phases by using a plurality of external clock signals having different phases, a plurality of code generators configured to receive a pair of selection clock signals determined from the plurality of clock signals and to output a phase code corresponding to a phase difference error between the pair of selection clock signals, and a delay circuit configured to at least partly simultaneously adjust at least two of a rising edge and a falling edge of each of the plurality of external clock signals with reference to the phase code during a lock time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.