Vertical semiconductor device and method for fabricating the same
US12369320B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2022 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | May 12, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
Abstract
A method for fabricating a vertical semiconductor device may include forming a lower-level stack including a source sacrificial layer over a semiconductor substrate; forming an upper-level stack including dielectric layers and sacrificial layers over the lower-level stack; forming a vertical channel structure including a channel layer that penetrates the upper-level stack and the lower-level stack; forming a slit that penetrates the upper-level stack while exposing the source sacrificial layer; forming a lateral recess that extends from the slit by removing the source sacrificial layer; forming a first contact layer which is coupled to a portion of the channel layer while filling the lateral recess; selectively forming a second contact layer over an exposed surface of the first contact layer; and selectively forming a chemical barrier layer over the second contact layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.