Encoding and compressing bits with Write-X feature in memory system
US12373129B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 7, 2023 |
| Grant date | Jul 29, 2025 |
| Priority date | — |
| Expiry date | Jul 7, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer host system, a system and method to compress the transmission between the central processing unit (CPU) and the dynamic random access memory (DRAM) of either of an extended consecutive series of ‘0’ bits or an extended consecutive series of ‘1’ bits. The CPU or a Compute Express Link (CXL) Initiator associated with the CPU identifies the consecutive strings of ‘0’ bits or ‘1’ bits. The CPU or the CXL Initiator sets data flags in a FLIT data structure, using just two bits or four bits to indicate the strings. The data structure is sent to a CXL memory, which interprets the flags and constructs the extended series of ‘0’ bits or extended series of ‘1’ bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.