Memory device, a controller for controlling the same, a memory system including the same, and an operating method of the same
US12373285B2 · kind B2 · utility
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3References
18Claims
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Key dates
| Filing date | Nov 20, 2023 |
| Grant date | Jul 29, 2025 |
| Priority date | — |
| Expiry date | Nov 20, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/106
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device including: a memory cell array including a plurality of memory cells disposed at intersections of wordlines and bitlines; an error correction circuit configured to read data from the memory cell array and to correct an error in the read data; and an error check and scrub (ECS) circuit configured to perform a scrubbing operation on the memory cell array, wherein the ECS circuit includes: a first register configured to store an error address obtained in the scrubbing operation; and a second register configured to store a page offline address received from an external device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.