Patent · US Active

Scheduling training of an inter-chiplet interface

US12373369B2 · kind B2 · utility

0Cited by
8References
21Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJun 29, 2022
Grant dateJul 29, 2025
Priority date
Expiry dateOct 2, 2042

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F2213/0026
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Systems and methods are disclosed for scheduling a data link training by a controller. The system and method include receiving an indication that a physical layer of a data link is not transferring data and initiating a training process of the physical layer of the data link in response to the indication that the physical layer of the data link is not transferring data. In one aspect, the indication that the physical layer of a data link is not transferring data is an indication that the physical layer of the data link is in a low power state. In another aspect, the indication that the physical layer of a data link is not transferring data is an indication that a data transfer has been completed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.