Virtual isolated pattern layer: isolated pattern recognition, extraction and compression
US12373628B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2024 |
| Grant date | Jul 29, 2025 |
| Priority date | — |
| Expiry date | Apr 29, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes identifying isolated shapes within a semiconductor design. The isolated shapes correspond to patterns of layers of components of the semiconductor design. The method also includes identifying one or more unique patterns among the isolated shapes, generating a virtual isolated pattern layer including data associated with the isolated shapes and the one or more unique patterns, determining whether a unique pattern of the one or more unique patterns satisfies a design rule based on the data of the virtual isolated pattern layer and producing an updated semiconductor design based on the determination that the unique pattern satisfies the design rule.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.