Quantum computer designs with core computing and cache regions that utilize lattice surgery
US12373726B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2021 |
| Grant date | Jul 29, 2025 |
| Priority date | — |
| Expiry date | May 29, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N10/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for performing lattice surgery without using twists is disclosed. Also, an error correcting code and decoder is provided that allows for error decoding of Pauli measurements performed in association with a lattice surgery operation. This allows for overall run-times of lattice surgery to be reduced. For example, some level of errors are tolerable, because they can be corrected, thus fewer measurement rounds (dm) may be performed for a given round of Pauli measurements. Additionally, a temporal encoding of lattice surgery technique is provided, which may additionally or alternatively be used to shorten run times. Also, a quantum computer layout is provided, wherein the layout includes a core computing region and a cache region. Also, protocols for swapping logical qubits between the core and cache are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.