Precharge circuitry for memory
US12374374B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 12, 2021 |
| Grant date | Jul 29, 2025 |
| Priority date | — |
| Expiry date | Sep 6, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a precharge circuitry for bit lines of an array of memory cells, the precharge circuitry comprising a precharge and limiting unit configured to precharge a first bit line and a second bit line, the precharge and limiting unit further configured to limit a first bit line precharge level of the first bit line and a second bit line precharge level of the second bit line during a precharge cycle of a read and/or write operation of any of the memory cells, wherein the precharge and limiting unit is configured to limit the first bit line precharge level and the second bit line precharge level in a single precharge cycle, preferably without substantial delay. The disclosure further relates to a memory comprising a plurality of memory cells arranged in columns and rows, and at least one precharge circuit, wherein the precharge circuit is connected to a first bit line and a second bit line of all memory cells within a column, wherein each precharge circuit is configured to limit the first bit line to a first bit line precharge level and the second bit line to a second bit line precharge level during a precharge cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.