Memory cell, electronic circuit comprising such cells, related programming method and multiplication and accumulation method
US12374397B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 10, 2023 |
| Grant date | Jul 29, 2025 |
| Priority date | — |
| Expiry date | Jan 31, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell, includes first and second main terminals, an auxiliary terminal; M memristor(s) between the main terminals, M≥1; M primary switch(es), each in parallel with a memristor; and a secondary switch between the second main terminal and the auxiliary terminal. It is configured for writing to at least one memristor by opening each primary switch in parallel with the at least one memristor, closing each other primary switch, closing the secondary switch and applying a corresponding programming voltage between the first main terminal and the auxiliary terminal; and for reading at least one memristor by opening each primary switch in parallel with the at least one memristor, closing each other possible primary switch, opening the secondary switch and measuring a corresponding electrical quantity between the main terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.