Optimized read current consumption based on lower page read information for non-volatile memory apparatus
US12374403B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2023 |
| Grant date | Jul 29, 2025 |
| Priority date | — |
| Expiry date | Feb 21, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory apparatus and method of operation are provided. The apparatus includes memory cells disposed in memory holes connected to bit lines. The memory cells retain a threshold voltage corresponding to data states. A control means applies a bit line voltage to the bit lines while determining whether the memory cells have the threshold voltage above one or more read levels associated with each of the data states in a first portion of a read operation. The control means groups the memory cells targeted for ones of the data states into data state groups based on the first portion of the read operation. The control means also supplies a near zero voltage to the bit lines coupled to the memory cells targeted for ones of the data states associated with at least one of the data state groups while reading the memory cells in subsequent portions of the read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.