Memory structures and methods of processing the same
US12376296B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 6, 2022 |
| Grant date | Jul 29, 2025 |
| Priority date | — |
| Expiry date | Apr 13, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosed technology generally relates to memory structures, for example for a vertical NAND memory. In one aspect, a memory structure includes a substrate and a layer stack arranged on a surface of the substrate, wherein the layer stack includes one or more conductive material layers alternating with one or more dielectric material layers. The memory structure can also include a trench in the layer stack, wherein the trench is formed through the one or more conductive material layers, and wherein the trench includes inner side walls. The memory structure also includes a programmable material layer arranged in the trench and which covers the inner side walls of the trench. The memory structure further includes an oxide semiconductor layer arranged in the trench over the programmable material layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.