Semiconductor devices and methods of manufacturing thereof
US12376358B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2021 |
| Grant date | Jul 29, 2025 |
| Priority date | — |
| Expiry date | Jun 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
Abstract
A method of fabricating a semiconductor device includes forming at least one fin on a substrate, a plurality of dummy gates over the at least one fin, and a sidewall spacer on the dummy gates. Source and drain regions are epitaxially formed contacting the at least one fin and laterally adjacent the dummy gates, where forming the source and drain regions leaves a void below the source and drain regions and adjacent the dummy gates. The dummy gates are replaced with active gates, each having a gate dielectric on the sidewall spacer and a gate electrode on the gate dielectric. A patterned layer is formed exposing a selected active gate of the active gates. A first etch is performed to remove exposed portions of the gate electrode of the selected active gate. A second etch is performed, after the first etch, to remove exposed portions of a gate dielectric of the selected active gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.