Mechanism for instruction fusion
US12379931B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2023 |
| Grant date | Aug 5, 2025 |
| Priority date | — |
| Expiry date | Nov 28, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30181
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compute node capable of enhanced performance and/or energy savings is proposed. The proposed compute node may check whether a last instruction of a first group—retrieved in a first decode cycle—is potentially a fusible instruction. If so, the proposed compute node may refrain from decoding the last instruction in the first decode cycle. Instead, the proposed compute node may determine if a first instruction of a second group of instructions retrieved in a second decode cycle (subsequent to the first decode cycle) is fusible with the last instruction of the first group. If so, the two instructions may be fused to a single micro-operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.