Condensed coherence directory entries for processing-in-memory
US12380029B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2022 |
| Grant date | Aug 5, 2025 |
| Priority date | — |
| Expiry date | Feb 11, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with the described techniques for condensed coherence directory entries for processing in memory, a computing device includes a core that includes a cache, a memory that includes multiple banks, a coherence directory that includes a condensed entry indicating that data associated with a memory address and the multiple banks is not stored in the cache, and a cache coherence controller. The cache coherence controller receives a processing-in-memory command to the memory address and performs a single lookup in the coherence directory for the processing-in-memory command based on inclusion of the condensed entry in the coherence directory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.