Patent · US Active

Refreshing cache regions using a memory controller and multiple tables

US12380033B2 · kind B2 · utility

0Cited by

2References

12Claims

0Family size

Assignee

CENTAUR TECHNOLOGY, INC. · US

Inventors

Douglas R. Reed · Austin, US
Al Loper · Austin, US
Terry Parks · Austin, US

Key dates

Filing date	Jan 21, 2022
Grant date	Aug 5, 2025
Priority date	—
Expiry date	Jan 29, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/401
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment, a controller in a microprocessor, the controller configured to manage accesses to dynamic random access memory (DRAM), the controller comprising: a first table configured to track cache lines that have been written to zero for a plurality of first memory regions; and a second table configured to track the cache lines that have been written to zero for a plurality of second memory regions, wherein each of the plurality of second memory regions comprises a group of the plurality of first memory regions where all of the cache lines within each of the plurality of the first memory regions within the group have been written to zero.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.