Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanism
US12380326B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2024 |
| Grant date | Aug 5, 2025 |
| Priority date | — |
| Expiry date | Mar 28, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/047
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus to facilitate processing of a sparse matrix for arbitrary graph data is disclosed. The apparatus includes a graphics processing unit having a data management unit (DMU) that includes a scheduler for scheduling matrix operations, an active logic for tracking active input operands, and a skip logic for tracking unimportant input operands to be skipped by the scheduler. Processing circuitry is coupled to the DMU. The processing circuitry comprises a plurality of processing elements including logic to read operands and a multiplication unit to multiply two or more operands for the arbitrary graph data and customizable circuitry to provide custom functions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.