Memory device, layout, and method
US12380957B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2021 |
| Grant date | Aug 5, 2025 |
| Priority date | — |
| Expiry date | Mar 18, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/25
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) device includes transistor and programmable structure regions. The transistor region includes a source structure configured to receive a reference voltage, a first portion of a drain structure, and a gate electrode positioned between the source structure and the first portion of the drain structure, and configured to receive an activation signal. The programmable structure region includes a second portion of the drain structure, a first signal line configured to receive an operational voltage, a second signal line, a gate via underlying and electrically connected to the first signal line, and a drain via positioned between and electrically connected to the second portion of the drain structure and the second signal line. Portions of the first signal line including a gate via location and the second signal line including a drain via location are positioned in parallel in a same metal layer of the IC device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.