Transistor structure using multiple two-dimensional channels
US12382652B2 · kind B2 · utility
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Key dates
| Filing date | Jun 7, 2023 |
| Grant date | Aug 5, 2025 |
| Priority date | — |
| Expiry date | Jul 24, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A transistor structure that includes multiple heterojunction layer sets, each generating a two-dimensional electron gas (2DEG), such that the transistor structure has a stack of 2DEGs that may be used to conduct between source and drain. A terminal is provided proximate an uppermost 2DEG to control whether the uppermost 2DEG is continuous between a source contact and a source plug. A source plug connects the uppermost 2DEG with the next 2DEG, and a drain plug also connects the uppermost 2DEG with the next 2DEG. Thus, the gate terminal may control the flow of current in sub-surface 2DEGs between the source and drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.