Epitaxial wafer and semiconductor memory device using the same
US12382672B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2022 |
| Grant date | Aug 5, 2025 |
| Priority date | — |
| Expiry date | Apr 12, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6735
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An epitaxial wafer and a semiconductor memory device, the epitaxial wafer including a semiconductor substrate having a front surface and a rear surface opposite to each other; a strain relaxed buffer (SRB) layer on and entirely covering the front surface of the semiconductor substrate; and a multi-stack on and entirely covering a surface of the SRB layer, wherein the SRB layer includes a silicon germanium (SiGe) epitaxial layer including germanium (Ge) at a first concentration of about 2.5 at % to about 18 at %, and the multi-stack has a superlattice structure in which a plurality of silicon (Si) layers and a plurality of SiGe layers are alternately provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.