Memory structure with optimized latch clock design
US12386383B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2023 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Feb 22, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is provided and includes a memory array, first to second latch circuits and a gating circuit. Read and write operations are triggered by first and second edges of an internal clock signal respectively. The first latch circuit generates a first output signal in response to an input signal and a first latch clock signal, a first edge of the first latch clock signal generated based on the first edge of the internal clock signal. The second latch circuit generates a second output signal in response to the first output signal and a second latch clock signal, a first edge of the second latch clock signal being between first and second edges of the first latch clock signal. The gating circuit generates, in response to the second output signal and a gating clock generated, a third output signal to the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.