Semiconductor package
US12388029B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2022 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Jul 12, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first package substrate having a lower surface and an upper surface respectively including a plurality of first lower surface pads and a plurality of first upper surface pads, a second package substrate having a lower surface and an upper surface respectively including a plurality of second lower surface pads and a plurality of second upper surface pads, wherein the plurality of second upper surface pads comprise all of the upper surface pads at the upper surface of the second package substrate, a semiconductor chip provided between the first package substrate and the second package substrate and attached onto the first package substrate, and a plurality of metal core structures connecting some of the plurality of first upper surface pads to some of the plurality of second lower surface pads and not vertically overlapping any of the plurality of second upper surface pads, each metal core structure having a metal core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.