Memory and forming method thereof
US12389588B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 29, 2022 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Dec 26, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
Abstract
The present disclosure relates to a memory and a forming method thereof. The method of forming a memory includes: forming a stacked layer on a surface of a substrate, the stacked layer including interlayer isolation layers arranged at intervals in a first direction and a sacrificial layer group located between adjacent two of the interlayer isolation layers, the sacrificial layer group including a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer sequentially stacked in the first direction, and the stacked layer including a transistor region, where the first direction is a direction perpendicular to a top surface of the substrate; removing the first sacrificial layer in the transistor region to form a first gap; forming an active pillar in the first gap; removing the second sacrificial layer and the third sacrificial layer in the transistor region to form a second gap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.