Semiconductor device structure with inner spacer layer
US12389619B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2024 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Mar 26, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device structure is provided. The semiconductor device structure includes forming semiconductor device structure includes a gate stack wrapping around a plurality of nanowire structures. The gate stack includes a first portion above the plurality of nanowire structures and second portions between the nanowire structures. The semiconductor device structure further includes a gate spacer layer along a sidewall of the first portion of the gate stack, and a plurality of inner spacer layers along sidewalls of the second portions of the gate stack. The gate spacer layer has a first carbon concentration, the inner spacer layers have a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.