Method for manufacturing a transistor with a gate-all-around structure
US12389644B2 · kind B2 · utility
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4References
15Claims
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Key dates
| Filing date | May 27, 2022 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Aug 23, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/832
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method for manufacturing a pFET transistor, the method for manufacturing the transistor including providing a base structure comprising a silicon channel and a gate structure, the gate structure surrounding the channel leaving two flanks of the channel free; growing a first layer made from silicon-germanium alloy on the flanks of the channel; enriching the channel with germanium atoms from the first layer; and forming a drain region and a source region on either side of the channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.