Transistors with stacked semiconductor layers as channels
US12389649B2 · kind B2 · utility
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4References
20Claims
0Family size
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Key dates
| Filing date | Feb 21, 2022 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Apr 27, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/834
Abstract
A method of forming a semiconductor device includes depositing a p-type semiconductor layer over a portion of a semiconductor substrate, depositing a semiconductor layer over the p-type semiconductor layer, wherein the semiconductor layer is free from p-type impurities, forming a gate stack directly over a first portion of the semiconductor layer, and etching a second portion of the semiconductor layer to form a trench extending into the semiconductor layer. At least a surface of the p-type semiconductor layer is exposed to the trench. A source/drain region is formed in the trench. The source/drain region is of n-type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.