Atomic instruction set and architecture with bus arbitration locking
US12393429B2 · kind B2 · utility
0Cited by
7References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 19, 2023 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Apr 19, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/366
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions. The instructions, when read and executed by a processor, cause the processor to identify a first input instruction in a code stream to be executed, determine that the first input instruction includes an atomic operation designation, and selectively block interrupts for a duration of execution of the first input instruction and a second input instruction. The second input instruction is to immediately follow the first input instruction in the code stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.