Method for generating a layout diagram of a semiconductor device including power-grid- adapted route-spacing
US12393762B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2021 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Dec 14, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5286
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of generating a layout diagram of a semiconductor device includes populating a conductive layer M(h) with segment patterns representing corresponding conductive segments in the semiconductor device. The segment patterns including first and second power grid (PG) patterns and first routing patterns, where h is an integer and h≥1. Arranging long axes of the first and second PG patterns and the first routing patterns to extend in a first direction. Arranging the first and second PG patterns to be separated, relative to a second direction, by a PG gap having a midpoint. The second direction being substantially perpendicular to the first direction. Distributing the first routing patterns between the first and second PG patterns and substantially uniformly in the second direction with respect to the midpoint of the PG gap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.