Pipeline delay elimination with parallel two level primitive batch binning
US12394010B2 · kind B2 · utility
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17References
20Claims
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Key dates
| Filing date | Dec 13, 2022 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Nov 13, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T17/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for rendering is provided. The technique includes for a set of primitives processed in a coarse binning pass, outputting early draw data to an early draw buffer; while processing the set of primitives in the coarse binning pass, processing the early draw data in a fine binning pass; and processing remaining primitives of the set of primitives in the fine binning pass.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.