Apparatuses and methods including dice latches in a semiconductor device
US12394456B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2023 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Feb 8, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one or more embodiments, an apparatus comprising a plurality of dice latches, dice latch control logic, and a plurality of data input logic is provided. The dice latches are coupled in parallel and latch respective data. The dice latch control logic receives a load control signal and a reset control signal, provides a reset signal and further provides first and second load signals to the dice latches. The reset signal is based on the reset control signal. The first and second load signals are based on the load control signal and the reset control signal. The data input logic each are coupled to a respective one of the dice latches. Each of the data input logic receives a precharge control signal and respective input data and further provides data and complementary data to the respective one of the dice latches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.