Hybrid FeRAM/OxRAM data storage circuit
US12394464B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2023 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Mar 15, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage circuit includes a first memory array comprising a plurality of FeRAM memory units; a second memory array comprising a plurality of OxRAM memory units; each of the first and second memory arrays comprising: a plurality of word lines, a plurality of source lines and a plurality of bit lines; for each column each memory unit comprising: a memory cell having a first electrode and a second electrode connected to the source line associated to the memory unit; a selection transistor having a gate connected to the word line associated to the memory unit and placed in series with the memory cell between the source line and a bit line associated to of the memory unit; the data storage circuit comprising further: a data transfer stage configured to transfer data from a set of source FeRAM memory units having a common bit line to a target OxRAM unit by converting a read signal from the common bit line to a transfer voltage applied on a target line of the target OxRAM unit; the target line corresponding to the word line or the source line and having the same direction as the common bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.